1. Field of the Invention
The present invention relates to a semiconductor device with a trench, the inner wall of which is covered with a dielectric material and which intends to reduce the capacitance, and a method for fabricating the same.
2. Description of the Related Art
Conventionally, a trench is used as a gate of a vertical MOS transistor such as a power MOSFET.
The trench has two types of structures, i.e. a V (shape)-trench and a U (shape)-trench. For example, as for the former, JP-A-55-48968 mainly relates to a horizontal MOS transistor, but discloses, (refer to FIG. 14 of the JP-A-55-48968), a vertical MOS transistor including a source region (21) formed around a V-trench gate and a drain region (26) of N.sup.- type layer disposed at a bottom of the V-trench, namely discloses a V-trench MOS transistor. On the other hand, the latter is disclosed in detail in JP-A-7-326741 and JP-A-7-263692.
For example, in the vertical MOS transistor disclosed in JP-A-7-263692, as shown in FIG. 12 of this application, an N.sup.- type semiconductor layer 10 is located on a N.sup.+ type semiconductor substrate (not shown) and a P type semiconductor layer 11 is formed on the N.sup.- type semiconductor layer 10. A trench 12 is formed from the surface of the semiconductor layer 11 so that the bottom and its vicinity is engaged in the N.sup.- type semiconductor layer 10.
The inner wall of the trench 12 is covered with a gate insulating layer 13. A conductive material such as polycrystalline silicon (poly-si) 14 is embedded in the trench 12. An N.sup.+ type source region 15 is formed around the trench 12. A source electrode 17 is formed through the source region 15 and an insulating film 16 surrounded by the source region 15 and formed to expose the surface of the P.sup.- type semiconductor layer.
The surface of the semiconductor layer outside the trench 12 between the source region 15 and the drain region 10 is inverted from P type into N type to form a channel so that a current flows from the source region 15 toward the drain side.
In (FIG. 14 of) JP-A-48968, a "V-MOS", having a trench of V-shape is shown. In the V-MOS", an electric field is concentrated into the bottom so that breakage is likely to occur between the gate and drain. In addition, dry etching is difficult to carry out for machining and hence wet etching is commonly adopted. Therefore, the slanting angle of the V-trench is defined according to a crystal face so that the size of the opening cannot be increased. Further, owing to variations in the depth of the trench, C.sub.gd varies greatly. This leads to variations in the switching speed.
On the other hand, the "U-trench" of the MOS transistor disclosed in JP-A-7-263692 is machined by dry etching and is a "Round" shape on the bottom. Therefore, unlike the V-trench, an electric field is prevented from being concentrated at the bottom. The capacitance C.sub.rss =C.sub.gd between a trench bottom and N.sup.- type layer, however, is increased, thus retarding the switching speed.
Further, JP-A-7-326741 intends to remove a LOCOS to form a trench, (as shown in its FIG. 2). However, because the oxidizing step is required, the depth of the trench cannot be increased. In addition, owing to the formation of a bird's beak, defects are likely to occur below the bird'sbeak. When the LOCOS is grown to a deep position in order to increase the channel length, a long oxidizing time is required. Correspondingly, a bird's beak is further grown, and the size of the opening of the trench is increased, thus increasing the capacitance. Further, the cell density cannot be increased and reduction of the on-resistance is difficult.
The present invention intends to solve these problems, particularly to reduce the capacitance and to realize high speed switching while preventing reduction of the cell density.
Assuming that the switching time of the transistor is T, T .varies..alpha. (C.sub.gs +C.sub.gd). C.sub.gs represents a gate-source capacitance. Since the source electrode is in contact with the P.sup.+ type semiconductor layer, it also represents the capacitance between the channel region and gate electrode. C.sub.gd represents a gate-drain capacitance.